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rt8803a 1 ds8803a-06 april 2011 www.richtek.com 2/3-phase pwm controller for high-density power supply general description the rt8803a is a 2/3-phase synchronous buck controller specifically designed to power intel ? / amd next generation microprocessors. it implements an internal 8-bit dac that is identified by vid code of microprocessor directly. rt8803a generates vid table that conform to intel ? vrd10.x and vrd11 core power with 6.25mv increments and 0.5% accuracy. rt8803a adopts innovative time-sharing dcr current sensing technique to sense phase currents for phase current balance, load line setting and over current protection. using a common gm to sense all phase currents eliminates offset and linearity variation between gms in conventional current sensing methods. as sub-milli-ohm-grade inductors are widely used in modern motherboards, slight offset and linearity mismatch will cause considerable current shift between phases. this technique ensures good current balance at mass production. other features include over current protection, programmable soft start, over voltage protection, and output offset setting. rt8803a comes to a small footprint package with vqfn-32l 5x5. features z z z z z 5v power supply z z z z z 2/3-phase power conversion with automatic phase selection z z z z z 8-bit vid interface, supporting intel vrd11/vrd10.x and amd k8, k8_m2 cpus z z z z z vr_hot and vr_fan indication z z z z z precision core voltage regulation z z z z z power stage thermal balance by dcr current sensing z z z z z adjustable soft-start z z z z z over-voltage protection z z z z z adjustable frequency and typical at 300khz per phase z z z z z power good indication z z z z z 32-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z intel ? /amd new generation microprocessor for desktop pc and motherboard z low output voltage, high power density dc-dc converters z voltage regulator modules ordering information pin configurations (top view) vqfn-32l 5x5 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pwm3 pwm2 pwm1 isp1 isp2 isp3 vtt/en vr_ready fbrtn fb comp ss vr_fan vr_hot tsen dvd rt ofs adj imax isn1 isn23 vid_sel vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 101112 14 13 28 27 26 25 24 22 23 32 31 30 29 gnd vid7 vdd 33 package type qv : vqfn-32l 5x5 (v-type) lead plating system p : pb free g : green (halogen free and pb free) rt8803a
rt8803a 2 ds8803a-06 april 2011 www.richtek.com typical application circuit 32 29 30 31 28 25 26 27 19 18 17 9 1872 12 5 4 20 21 22 11 14 6 15 13 16 23 24 10 10k 10k 10k btx_5v pgood nc nc 0.1uf 0 0 12k 56nf 5.6pf 470pf 2.2nf 15k 1.5k btx_12v btx_5v vid_sel vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 10 0.1uf 10k 1.1k 3 cpu_vss cpu_vcc 75k 360 360 75k 360 360 360 1uf 1uf 1uf 100 gnd isp2 isp3 isp1 isn23 dvd rt ofs adj imax comp isn1 fb vtt/en vr_ready fbrtn pwm2 pwm1 ss vr_fan vr_hot tsen vid_sel vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vdd pwm3 rt8803a v core 23 v core 1 vtt r1 r2 r3 r4 r5 r6 r8 r9 r10 r12 r13 r11 r15 r16 r18 r20 r21 r22 r17 r23 r24 r26 r19 c1 c2 c3 c4 c5 c6 c7 c8 c92 c10 nc r25 r14 btx_5v for amd for intel vddio for k8 gnd for k8_m2 enable for intel for amd vddio btx_5v r7 56nf 300 300 8.2k vcc vin pgnd boot ugate phase lgate rt9619 1 8 7 5 6 2 4 l3 1uf 0.1uf 10 btx_12v 4.7uf 1200uf 2.2 3.3nf 1n4148 nc 3 4.7uf 4.7uf q7 q8 q9 v core 23 r31 r32 c25 c26 c27 c28 c29 c30 c31 ipd09n03la ips06n03la 10k rt1 ntc 280nh vcc vin pgnd boot ugate phase lgate rt9619 1 8 7 5 6 2 4 l2 v in 1uf 0.1uf 10 btx_12v 4.7uf 1200uf 2.2 3.3nf 1n4148 nc 3 4.7uf 4.7uf q4 q5 q6 v core 23 r29 r30 c18 c19 c20 c21 c22 c23 c24 v in 10uf x 18 v cc v ss c32 to c41 560uf x 10 c42 to c59 ipd09n03la ips06n03la 280nh vcc pwm pgnd boot ugate phase lgate rt9619 1 8 7 5 6 2 4 l1 btx_12v 1uf 0.1uf 10 v in btx_12v 4.7uf 1200uf 2.2 3.3nf 1n4148 nc 3 4.7uf 4.7uf q1 q2 q3 v core 1 ipd09n03la r27 r28 c11 c12 c13 c14 c15 c16 c17 ips06n03la ntc rt2 2k 280nh r33
rt8803a 3 ds8803a-06 april 2011 www.richtek.com functional pin description vtt/en (pin 1) the pin is defined as the chip enable, and the vtt is applied for internal vid pull high power and power sequence monitoring. vr_ready (pin 2) power good open-drain output. fbrtn (pin 3) feedback return pin. vid dac and error amplifier reference for remote sensing of the output voltage. fb (pin 4) inverting input pin of the internal error amplifier. comp (pin 5) output pin of the error amplifier and input pin of the pwm comparator. ss (pin 6) connect this ss pin to gnd with a capacitor to set the soft-start time interval. vr_fan (pin 7) the pin is defined to signal vr thermal information for external vr thermal dissipation scheme triggering. vr_hot (pin 8) the pin is defined to signal vr thermal information for external vr thermal dissipation scheme triggering. tsen (pin 9) temperature detect pin for vr_hot and vr_fan. dvd (pin 10) programmable power uvlo detection input. trip threshold is 1v at v dvd rising. rt (pin 11) the pin is defined to set internal switching operation frequency. connect this pin to gnd with a resistor r rt to set the frequency f sw . ofs (pin 12) the pin is defined for load line offset setting. adj (pin 13) current sense output for active droop adjusting. connect a resistor from this pin to gnd to set the load droop. imax (pin 14) the pin is defined to set threshold of over current. isn1 (pin 15) current sense negative input pin for channel 1 current sensing. isn23 (pin 16) current sense negative input pins for channel 2 and channel 4 current sensing. isp1 (pin 19), i sp2 (pin 18), isp3 (pin 17) current sense positive input pins for individual converter channel current sensing. pwm1 (pin 20), pwm2 (pin 21), pwm3 (pin 22) pwm outputs for each driven channel. connect these pins to the pwm input of the mosfet driver. for systems which using 2/3/4 channels, pull pwm 3/4/5 pins up to high. vdd (pin 23) ic power supply. connect this pin to a 5v supply. vid7 (pin 24), vid6 (pin 25), vid5 (pin 26), vid4 (pin 27), vid3 (pin 28), vid2 (pin 29), vid1 (pin 30), vid0 (pin 31), vid_sel (32) dac voltage identification inputs for vrd10.x / vrd11 / k8 / k8_m2 . these pins are internally pulled up to vtt. gnd [exposed pad (33)] the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. vidsel vid [7] table vtt x vr11 gnd x vr10.x vdd nc k8 vdd gnd k8_m2 3500 r e 4.463 f rt sw 9 + =
rt8803a 4 ds8803a-06 april 2011 www.richtek.com function block diagram oscillator & ramp generator sample & hold pwm1 pwm2 pwm3 droop tune & hi-i detection current processing sum/n & ocp detection dac vid4 vid2 vid1 vid0 vid5 vid3 vr_fan fbrtn vr_ready tsen gnd soft start & pgood - + + - isp1 isp2 isp3 pulse width modulator & output buffer mux mux temperature processing power on reset ss fb ea csa comp adj vid_sel clamp imax vid6 vid7 ofs vr_hot rt dvd vtt/en vdd mux isn1 isn23
rt8803a 5 ds8803a-06 april 2011 www.richtek.com table 1. output voltage program (vrd10.x + vid6) to be continued pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 0 1 0 1 0 1 1 1.60000v 0 1 0 1 0 1 0 1.59375v 0 1 0 1 1 0 1 1.58750v 0 1 0 1 1 0 0 1.58125v 0 1 0 1 1 1 1 1.57500v 0 1 0 1 1 1 0 1.56875v 0 1 1 0 0 0 1 1.56250v 0 1 1 0 0 0 0 1.55625v 0 1 1 0 0 1 1 1.55000v 0 1 1 0 0 1 0 1.54375v 0 1 1 0 1 0 1 1.53750v 0 1 1 0 1 0 0 1.53125v 0 1 1 0 1 1 1 1.52500v 0 1 1 0 1 1 0 1.51875v 0 1 1 1 0 0 1 1.51250v 0 1 1 1 0 0 0 1.50625v 0 1 1 1 0 1 1 1.50000v 0 1 1 1 0 1 0 1.49375v 0 1 1 1 1 0 1 1.48750v 0 1 1 1 1 0 0 1.48125v 0 1 1 1 1 1 1 1.47500v 0 1 1 1 1 1 0 1.46875v 1 0 0 0 0 0 1 1.46250v 1 0 0 0 0 0 0 1.45625v 1 0 0 0 0 1 1 1.45000v 1 0 0 0 0 1 0 1.44375v 1 0 0 0 1 0 1 1.43750v 1 0 0 0 1 0 0 1.43125v 1 0 0 0 1 1 1 1.42500v 1 0 0 0 1 1 0 1.41875v 1 0 0 1 0 0 1 1.41250v 1 0 0 1 0 0 0 1.40625v 1 0 0 1 0 1 1 1.40000v 1 0 0 1 0 1 0 1.39375v 1 0 0 1 1 0 1 1.38750v 1 0 0 1 1 0 0 1.38125v 1 0 0 1 1 1 1 1.37500v 1 0 0 1 1 1 0 1.36875v 1 0 1 0 0 0 1 1.36250v
rt8803a 6 ds8803a-06 april 2011 www.richtek.com pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 1 0 1 0 0 0 0 1.35625v 1 0 1 0 0 1 1 1.35000v 1 0 1 0 0 1 0 1.34375v 1 0 1 0 1 0 1 1.33750v 1 0 1 0 1 0 0 1.33125v 1 0 1 0 1 1 1 1.32500v 1 0 1 0 1 1 0 1.31875v 1 0 1 1 0 0 1 1.31250v 1 0 1 1 0 0 0 1.30625v 1 0 1 1 0 1 1 1.30000v 1 0 1 1 0 1 0 1.29375v 1 0 1 1 1 0 1 1.28750v 1 0 1 1 1 0 0 1.28125v 1 0 1 1 1 1 1 1.27500v 1 0 1 1 1 1 0 1.26875v 1 1 0 0 0 0 1 1.26250v 1 1 0 0 0 0 0 1.25625v 1 1 0 0 0 1 1 1.25000v 1 1 0 0 0 1 0 1.24375v 1 1 0 0 1 0 1 1.23750v 1 1 0 0 1 0 0 1.23125v 1 1 0 0 1 1 1 1.22500v 1 1 0 0 1 1 0 1.21875v 1 1 0 1 0 0 1 1.21250v 1 1 0 1 0 0 0 1.20625v 1 1 0 1 0 1 1 1.20000v 1 1 0 1 0 1 0 1.19375v 1 1 0 1 1 0 1 1.18750v 1 1 0 1 1 0 0 1.18125v 1 1 0 1 1 1 1 1.17500v 1 1 0 1 1 1 0 1.16875v 1 1 1 0 0 0 1 1.16250v 1 1 1 0 0 0 0 1,15625v 1 1 1 0 0 1 1 1.15000v 1 1 1 0 0 1 0 1.14375v 1 1 1 0 1 0 1 1.13750v 1 1 1 0 1 0 0 1.13125v 1 1 1 0 1 1 1 1.12500v 1 1 1 0 1 1 0 1.11875v table 1. output voltage program (vrd10.x + vid6) to be continued
rt8803a 7 ds8803a-06 april 2011 www.richtek.com pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 1 1 1 1 0 0 1 1.11250v 1 1 1 1 0 0 0 1.10625v 1 1 1 1 0 1 1 1.10000v 1 1 1 1 0 1 0 1.09375v 1 1 1 1 1 0 1 off 1 1 1 1 1 0 0 off 1 1 1 1 1 1 1 off 1 1 1 1 1 1 0 off 0 0 0 0 0 0 1 1.08750v 0 0 0 0 0 0 0 1.08125v 0 0 0 0 0 1 1 1.07500v 0 0 0 0 0 1 0 1.06875v 0 0 0 0 1 0 1 1.06250v 0 0 0 0 1 0 0 1.05625v 0 0 0 0 1 1 1 1.05000v 0 0 0 0 1 1 0 1.04375v 0 0 0 1 0 0 1 1.03750v 0 0 0 1 0 0 0 1.03125v 0 0 0 1 0 1 1 1.02500v 0 0 0 1 0 1 0 1.01875v 0 0 0 1 1 0 1 1.01250v 0 0 0 1 1 0 0 1.00625v 0 0 0 1 1 1 1 1.00000v 0 0 0 1 1 1 0 0.99375v 0 0 1 0 0 0 1 0.98750v 0 0 1 0 0 0 0 0.98125v 0 0 1 0 0 1 1 0.97500v 0 0 1 0 0 1 0 0.96875v 0 0 1 0 1 0 1 0.96250v 0 0 1 0 1 0 0 0.95625v 0 0 1 0 1 1 1 0.95000v 0 0 1 0 1 1 0 0.94375v 0 0 1 1 0 0 1 0.93750v 0 0 1 1 0 0 0 0.93125v 0 0 1 1 0 1 1 0.92500v 0 0 1 1 0 1 0 0.91875v 0 0 1 1 1 0 1 0.91250v 0 0 1 1 1 0 0 0.90625v 0 0 1 1 1 1 1 0.90000v to be continued table 1. output voltage program (vrd10.x + vid6)
rt8803a 8 ds8803a-06 april 2011 www.richtek.com pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 0 0 1 1 1 1 0 0.89375v 0 1 0 0 0 0 1 0.88750v 0 1 0 0 0 0 0 0.88125v 0 1 0 0 0 1 1 0.87500v 0 1 0 0 0 1 0 0.86875v 0 1 0 0 1 0 1 0.86250v 0 1 0 0 1 0 0 0.85625v 0 1 0 0 1 1 1 0.85000v 0 1 0 0 1 1 0 0.84375v 0 1 0 1 0 0 1 0.83750v 0 1 0 1 0 0 0 0.83125v table 1. output voltage program (vrd10.x + vid6)
rt8803a 9 ds8803a-06 april 2011 www.richtek.com pin name hex nominal output voltage dacout 00 off 01 off 02 1.60000v 03 1.59375v 04 1.58750v 05 1.58125v 06 1.57500v 07 1.56875v 08 1.56250v 09 1.55625v 0a 1.55000v 0b 1.54375v 0c 1.53750v 0d 1.53125v 0e 1.52500v 0f 1.51875v 10 1.51250v 11 1.50625v 12 1.50000v 13 1.49375v 14 1.48750v 15 1.48125v 16 1.47500v 17 1.46875v 18 1.46250v 19 1.45625v 1a 1.45000v 1b 1.44375v 1c 1.43750v 1d 1.43125v 1e 1.42500v 1f 1.41875v 20 1.41250v 21 1.40625v 22 1.40000v 23 1.39375v 24 1.38750v 25 1.38125v 26 1.37500v to be continued table 2. output voltage program (vrd11) pin name hex nominal output voltage dacout 27 1.36875v 28 1.36250v 29 1.35625v 2a 1.35000v 2b 1.34375v 2c 1.33750v 2d 1.33125v 2e 1.32500v 2f 1.31875v 30 1.31250v 31 1.30625v 32 1.30000v 33 1.29375v 34 1.28750v 35 1.28125v 36 1.27500v 37 1.26875v 38 1.26250v 39 1.25625v 3a 1.25000v 3b 1.24375v 3c 1.23750v 3d 1.23125v 3e 1.22500v 3f 1.21875v 40 1.21250v 41 1.20625v 42 1.20000v 43 1.19375v 44 1.18750v 45 1.18125v 46 1.17500v 47 1.16875v 48 1.16250v 49 1.15625v 4a 1.15000v 4b 1.14375v 4c 1.13750v 4d 1.13125v
rt8803a 10 ds8803a-06 april 2011 www.richtek.com pin name hex nominal output voltage dacout 4e 1.12500v 4f 1.11875v 50 1.11250v 51 1.10625v 52 1.10000v 53 1.09375v 54 1.08750v 55 1.08125v 56 1.07500v 57 1.06875v 58 1.06250v 59 1.05625v 5a 1.05000v 5b 1.04375v 5c 1.03750v 5d 1.03125v 5e 1.02500v 5f 1.01875v 60 1.01250v 61 1.00625v 62 1.00000v 63 0.99375v 64 0.98750v 65 0.98125v 66 0.97500v 67 0.96875v 68 0.96250v 69 0.95625v 6a 0.95000v 6b 0.94375v 6c 0.93750v 6d 0.93125v 6e 0.92500v 6f 0.91875v 70 0.91250v 71 0.90625v 72 0.90000v 73 0.89375v 74 0.88750v pin name hex nominal output voltage dacout 75 0.88125v 76 0.87500v 77 0.86875v 78 0.86250v 79 0.85625v 7a 0.85000v 7b 0.84375v 7c 0.83750v 7d 0.83125v 7e 0.82500v 7f 0.81875v 80 0.81250v 81 0.80625v 82 0.80000v 83 0.79375v 84 0.78750v 85 0.78125v 86 0.77500v 87 0.76875v 88 0.76250v 89 0.75625v 8a 0.75000v 8b 0.74375v 8c 0.73750v 8d 0.73125v 8e 0.72500v 8f 0.71875v 90 0.71250v 91 0.70625v 92 0.70000v 93 0.69375v 94 0.68750v 95 0.68125v 96 0.67500v 97 0.66875v 98 0.66250v 99 0.65625v 9a 0.65000v 9b 0.64375v to be continued table 2. output voltage program (vrd11)
rt8803a 11 ds8803a-06 april 2011 www.richtek.com pin name hex nominal output voltage dacout 9c 0.63750v 9d 0.63125v 9e 0.62500v 9f 0.61875v a0 0.61250v a1 0.60625v a2 0.60000v a3 0.59375v a4 0.58750v a5 0.58125v a6 0.57500v a7 0.56875v a8 0.56250v a9 0.55625v aa 0.55000v ab 0.54375v ac 0.53750v ad 0.53125v ae 0.52500v af 0.51875v b0 0.51250v b1 0.50625v b2 0.50000v b3 x b4 x b5 x b6 x b7 x b8 x b9 x ba x bb x bc x bd x be x bf x c0 x c1 x c2 x pin name hex nominal output voltage dacout c3 x c4 x c5 x c6 x c7 x c8 x c9 x ca x cb x cc x cd x ce x cf x d0 x d1 x d2 x d3 x d4 x d5 x d6 x d7 x d8 x d9 x da x db x dc x dd x de x df x e0 x e1 x e2 x e3 x e4 x e5 x e6 x e7 x e8 x e9 x to be continued table 2. output voltage program (vrd11)
rt8803a 12 ds8803a-06 april 2011 www.richtek.com pin name hex nominal output voltage dacout ea x eb x ec x ed x ee x ef x f0 x f1 x f2 x f3 x f4 x f5 x f6 x f7 x f8 x f9 x fa x fb x fc x fd x fe off ff off table 2. output voltage program (vrd11) note: (1) 0 : connected to gnd (2) 1 : open (3) x : don ' t care
rt8803a 13 ds8803a-06 april 2011 www.richtek.com table 3. output voltage program (k8) vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.200 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 shutdown note: (1) 0 : connected to gnd (2) 1 : open
rt8803a 14 ds8803a-06 april 2011 www.richtek.com table 4. output voltage program (k8_m2) to be continued pin name vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500
rt8803a 15 ds8803a-06 april 2011 www.richtek.com note: (1) 0 : connected to gnd (2) 1 : open (3) the voltage above are load independent for desktop and server platforms. for mobile platforms the voltage above correspond to zero load current. table 4. output voltage program (k8_m2) pin name vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750
rt8803a 16 ds8803a-06 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------ 7v z input, output or i/o voltage -------------------------------------------------------------------------------- gnd - 0.3v to v dd +0.3v z power dissipation, p d @ t a = 25 c vqfn ? 32l 5x5 ------------------------------------------------------------------------------------------------ 2.778w z package thermal resistance (note 2) vqfn-32l 5x5, ja ------------------------------------------------------------------------------------------- 36 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range -------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply voltage, v dd ------------------------------------------------------------------------------------------ 5v 10% z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics to be continued parameter symbol test conditions min typ max unit v dd supply current nominal supply current i dd pwm 1,2,3 open -- 12 16 ma power-on reset por threshold v ddrth v dd rising 4.0 4.2 4.5 v hysteresis v ddhys 0.2 0.5 -- v trip (low to high) v dvdth enable 0.9 1.0 1.1 v v dvd threshold hysteresis v dvdhys -- 60 -- mv trip (low to high) v ttth enable 0.75 0.85 0.95 v tt threshold hysteresis v tthys -- 0.1 -- v oscillator free running frequency f osc r rt = 20k 180 200 220 khz frequency adjustable range f osc_adj 50 -- 400 khz ramp amplitude v osc r rt = 20k -- 1.9 -- v ramp valley v rv 0.7 1.0 -- v maximum on-time of each channel three phase operation 62 67 72 % rt pin voltage v rt r rt = 20k 0.9 1.0 1.1 v (v dd = 5v, t a = 25 c, unless otherwise specified)
rt8803a 17 ds8803a-06 april 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. p arameter symbol test conditions min typ max u nit reference and dac v dac 1v ? 0.5 -- 0.5 % 1v v dac 0.8v ? 5 -- 5 mv dacout voltage accuracy v dac v dac < 0.8v ? 8 -- 8 mv dac (vid0-vid125) input low v ildac -- -- 1/2v tt ? 0.2 v dac (vid0-vid125) input high v ihdac 1/2v tt + 0.2 -- -- v v id pull-up resistance 12 15 18 k ofs pin voltage v ofs r ofs = 100k 0.9 1.0 1.1 v error amplifier dc gain -- 65 -- db gain-bandwidth product gbw -- 10 -- mhz slew rate sr comp = 10pf -- 8 -- v/ s current sense gm amplifier csn full scale source current i ispfss 100 -- -- a csn current for ocp 150 -- -- a protection over-voltage trip (fb-dacout) ovt 100 150 200 mv imax voltage v imax r imax = 20k 0.9 1.0 1.1 v power good output low voltage v pgoodl i pgood = 4ma -- -- 0.2 v
rt8803a 18 ds8803a-06 april 2011 www.richtek.com typical operating characteristics frequency vs. r rt 0 100 200 300 400 500 600 700 0 102030405060708090100 r rt (k [ ) frequency (khz) (k ) output voltage vs. temperature 1.248 1.25 1.252 1.254 1.256 1.258 1.26 1.262 1.264 -20 0 20 40 60 80 100 temperature output voltage (v) ( c) frequency vs. temperature 304 306 308 310 312 314 316 318 320 322 -20 0 20 40 60 80 100 temperature frequency (khz) ( c) power on from dvd dvd (1v/div) time (1ms/div) v out (1v/div) ss (1v/div) phase 3 (10v/div) power off from dvd dvd (1v/div) time (1 s/div) v out (1v/div) ss (1v/div) phase 3 (10v/div) gm 0 50 100 150 200 250 300 350 400 450 0 25 50 75 100 125 150 175 200 isn (ua) positive duty (ns) phase 3 phase 1 phase 2
rt8803a 19 ds8803a-06 april 2011 www.richtek.com power on with ocp ss (2v/div) time (500 s/div) pwm (5v/div) vr_ready (1v/div) v out 1v/div) output short circuit ss (2v/div) time (1ms/div) pwm (5v/div) vr_ready (1v/div) v out (1v/div) power on from vcc12 vcc12 (10v/div) time (1ms/div) v out (1v/div) ss (1v/div) phase 3 (10v/div) power off from vcc12 vcc12 (10v/div) time (1ms/div) v out (1v/div) ss (1v/div) phase 3 (10v/div) power off from vcc5 vcc5 (5v/div) time (25ms/div) v out (1v/div) ss (1v/div) phase 3 (10v/div) power on from vcc5 vcc5 (5v/div) time (1ms/div) v out (1v/div) ss (1v/div) phase 3 (10v/div)
rt8803a 20 ds8803a-06 april 2011 www.richtek.com dynamic vid v out (200mv/div) time (50 s/div) vid0 (500mv/div) dynamic vid v out (200mv/div) time (50 s/div) vid0 (500mv/div) ovp ss (2v/div) time (10 s/div) pwm (5v/div) vr_ready (1v/div) fb (1v/div) v out droop v out (20mv/div) time (2 s/div) i out ( 40a /div) v out overshoot time (2 s/div) v out (20mv/div) i out ( 40a /div)
rt8803a 21 ds8803a-06 april 2011 www.richtek.com applications information rt8803a is a multi-phase dc/dc controller specifically designed to deliver high quality power for next generation cpu. rt8803a controls a special power-on sequence & monitors the thermal condition of vr module to meet the vrd11 requirement. phase currents are sensed by innovative time-sharing dcr current sensing technique for channel current balance, droop tuning, and over current protection. using one common gm amplifier for current sensing eliminates offset errors and linearity variation between gms. as sub-milli-ohm-grade inductors are widely used in modern mother boards, slight mismatch of gm amplifiers offset and linearity results in considerable current shift between phases. the time-sharing dcr current sensing technique is extremely important to guarantee phase current balance in mass production. converter initialization, phase selection, and power good function the rt8803a initiates only after 3 pins are ready: vdd pin power on res et (por), vtt/en pin enabled, and dvd pin is higher than 1v. vdd por is to make sure rt8803a is powered by a voltage for normal work. the rising threshold voltage of vdd por is 4.2v typically. at vdd por, rt8803a checks pwm3, pwm4 and pwm5 status to determine phase number of operation. pull high pwm3 for two-phase operation; pull high pwm4 for three-phase operation; pull high pwm5 for four-phase operation. the unused current sense pins should be connected to gnd or left floating. vtt/en acts as a chip enable pin and receives signal from fsb or other power management ic. dvd is to make sure that atx12v is ready for drivers to work normally. connect a voltage divider from atx12v to dvd pin as shown in the typical application circuit. make sure that dvd pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum atx12v during normal operation. if any one of vdd, vtt/en, and dvd is not ready, rt8803a keeps its pwm outputs high impedance and the companion drivers turn off both upper and lower mosfets. after vdd, vtt/en, and dvd are ready, rt8803a initiates its soft start cycle that is compliant with intel ? vrd11 specification as shown in figure 1. a time-variant internal current source charges the capacitor connected to ss pin. ss voltage ramps up piecewise linearly and locks vid_dac output with a specified voltage drop. consequently, v core is built up according to vid_dac output and meet intel ? vrd11 requirement. vr_ready output is pulled high by external resistor when v core reaches vid_dac output with 1~2ms delay. an ss capacitor about 47nf is recommend for vrd11 compliance. voltage control cpu v core voltage is kelvin sensed by fb and fbrtn pins and precisely regulated to vid_dac output by internal high gain error amplifier (ea). the sensed signal is also used for power good and over voltage function. the typical ovp trip point is 170mv above vid_dac output. rt8803a pulls pwm outputs low and latches up upon ovp trip to prevent damaging the cpu. it can only restart by resetting one of vdd, dvd, or vtt/en pin. rt8803a suppo rts intel vr d10.x, vrd11, amd k8 and amd k8_m2 vid specification. the change of vid_dac output at vid on the fly is also smoothed by capacitor connected to ss pin. consequently, vcore shifts to its new position smoothly as shown in figure 2. figure 1. timming diagram during soft start interval 1~2ms 1~2ms 1~2ms 1~2ms vr_ready v core ss 1.1v vdd por, dvd, and vtt/en ready vid on the fly 1~2ms
rt8803a 22 ds8803a-06 april 2011 www.richtek.com consequently, the sensing current i x is proportional to inductor current i lx and is expressed as : the sensed current i x is used for current balance and droop tuning as described as followe d. since all phases share one common gm, gm offset and linearity variation effect is eliminated in practical applications. as sub-milli-ohm- grade inductors are widely used in modern mother boards, slight mismatch of gm amplifiers offset and linearity results in considerable current shift between phases. the time- sharing dcr current sensing technical is extremely important to guarantee phase current balance in mass production. phase current balance the sampled and held phase current i x are summed and averaged to get the averaged current . each phase current i x then is compared with the averaged current. the difference between i x and is injected to corresponding pwm comparator. if phase current i x is smaller than the averaged current , rt8803a increases the duty cycle of corresponding phase to increase the phase current accordingly and vice versa. x i x i figure 2. vcore response at vid on the fly v core vid7 pwm3 dcr current sensing rt8803a adopts an innovative time-sharing dcr current sensing technique to sense the phase currents for phase current balance (phase thermal balance) and load line regulation as shown in figure 3. current sensing amplifier gm samples and holds voltages vcx across the current sensing capacitor cx by turns in a switching cycle. according to the basic circuit theory, if figure 3 dcrx i vcx then cx rx dcrx lx lx = = csnx lx x r dcrx i i = csa r csn1 r csn3 r csn2 t1 t3 t2 t1 t3 t2 csa: current sense amplifier i x i x = i lx x dcr x /r csnx t1 t2 t3 isp1 isn1 isp3 isn23 isp2 isn23 s/h ckt + - l1 dcr1 l2 dcr2 l3 dcr3 r1 c1 + vc1 - r3 c3 + vc3 - r2 c2 + vc2 -
rt8803a 23 ds8803a-06 april 2011 www.richtek.com if with other phase kept unchanged, this phase would share (r px +rx)/r px times current than other phases. figure 6 and 7 show different current ratio setting for the power stage when phase 3 is programmed 2 times current than other phases. figure 8 and 9 compare the above current ratio setting results. output voltage offset function to meet intel ? requirement of initial offset of load line, rt8803a provides programmable initial offset function. external resistor r ofs and voltage source at ofs pin generate offset current , where v ofs is 1v typical. one quarter of i ofs flows through r fb1 as shown in figure 4. error amplifier would hold the inverting pin equal to v dac - v adj . thus output voltage is subtracted from v dac - v adj for a constant offset voltage. a positive output voltage offset is possible by connecting r ofs to vdd instead of to gnd. please note that when r ofs is connected to vdd, v ofs is v dd ? 2v typically and half of i ofs flows through r fb1 . v core is rewritten as : current ratio setting current ratio adjustment is possible as described below. it is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. figure 5 shows the application circuit of gm for current ratio requirement. according to basic circuit theory figure 7. gm1~2 setting for current ratio function figure 6. gm3 setting for current ratio function figure 4. load line and offset function figure 5 ofs ofs ofs r v i = ofs fb1 adj dac core r 4 r v v v ? ? = ofs fb1 adj dac core r r v v v + ? = dcrx i 1 r rx cx r srx r rx r vcx lx px px px px + + + = dcrx i r rx r vcx then cx ) //r (r dcrx l lx px px px x x + = = t l x dcrx i lx v out rx cx vcx +- r px + - + + - v core r fb1 dac r adj x 4i v adj 4 i ofs ea comp
rt8803a 24 ds8803a-06 april 2011 www.richtek.com figure 8 figure 10 load line without dead zone at light loads 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.3 1.31 0 5 10 15 20 25 i out (a) v core (v) r csn open r csn2 = 82k w/o dead zone compensation w/i dead zone compensation dead zone elimination rt8803a samples and holds inductor current at 50% period by time-sharing sourcing a current i x to r csn . at light load condition when inductor current is not balance, voltage vcx across the sensing capacitor would be negative. it needs a negative i x to sense the voltage. however, rt8803a cannot provide a negative i x and consequently cannot sense negative inductor current. this results in dead zone of load line performance as shown in figure 10. therefore a technique as shown in figure 11 is required to eliminate the dead zone of load line at light load condition. referring to figure 11, i x is expressed as : where i lx_50% is the of inductor current at 50% period. to make sure rt8803a could sense the inductor current, right hand side of equation (1) should always be positive: since r csn >> dcrx in pra ctical application, equation (2) could be simplified as : figure 11. application circuit o f gm (2) (1) csn lx_66% csn2 lx_66% csn2 out x r dcrx i r dcrx i r v i + + = 0 r dcrx i r dcrx i r v csn lx_66% csn2 lx_66% csn2 out + + csn lx_66% csn2 out r dcrx i r v r csn gmx ix + - r csn2 i lx lx dcrx rx cx vcx +- v out figure 9 current balance function 0 5 10 15 20 25 30 35 0 20406080100120 i out (a) i l (a) i l1 i l3 i l2 current ratio function 0 5 10 15 20 25 30 35 0 153045607590 i out (a) i l (a) i l3 i l2 i l1
rt8803a 25 ds8803a-06 april 2011 www.richtek.com for example, assuming the negative inductor current is i lx_50% = ? 5a at no load, then for r csn 330 , r adj = 160 , v out = 1.300v r csn2 85.8k choose r csn2 = 82k figure 10 shows that dead zone of load line at light load is eliminated by applying this technique. vr_hot & vr_fan setting figure 12 load line setting and thermal compensation v adj = sum(i x ) x r adj = (dcr x r adj / r csn ) x i out = ll x i out v out = v dac ? v adj = v dac ? ll x i out ll = dcr(ptc) x r adj (ntc) / r csn dcr is the inductor dcr which is a ptc resistance. ? 330 1m 5a r 1.3v csn2 q1 q2 q3 + - + - + - cmp cmp cmp 0.39 x v cc 0.33 x v cc 0.28 x v cc tsen r1 r ntc v cc 5v v tsen r1 r2 r ntc adj r adj figure 14. r adj connection for thernal compensation temperature v tsen vr_fan vr_hot 0.28 x v cc 0.33 x v cc 0.39 x v cc v tsen is inversely proportional to temperature. figure 13. vr_hot and vr_fan signal vs tsen voltage if r adj is connected as in figure 14, r adj = r1 + (r2// r ntc ), which is a negative temperature correlated resistance. by properly selecting r1 and r2, the positive temperature coefficient of dcr can be canceled by the negative temperature coefficient of r adj . thus the load line will be thermally compensated. over current protection phase current ocp rt8803a uses an external resistor r imax connected to imax pin to generate a reference current i imax for over current protection : where v imax is typical 1.0v . ocp comparator compares each sensed phase current i x with this reference current as shown in figure 15. equivalently, the maximum phase current i lx(max) is calculated as below: imax imax imax r v i = lx csnx imax imax x csnx x lx(max) imax imax imax x(max) imax x(max) r r r v 2 3 dcr r i i r v 2 3 i 2 3 i i 2 1 i 3 1 = = = = = figure 15. over current comparator + - 1/3 i x 1/2 i imax ocp comparator
rt8803a 26 ds8803a-06 april 2011 www.richtek.com error amplifier characteristic for fast response of converter to meet stringent output current transient response, rt8803a provides large slew rate capability and high gain-bandwidth performance. figure 18. gain-bandwidth measurement by signal a divided by signal b + - ea 4.7k b a v ref 4.7k figure 17. ea falling transient with 10pf loading ; slew rate = 8v/ s figure 16. ea rising transient with 10pf loading ; slew rate = 10v/ s design procedure suggestion a. output filter pole and zero (inductor, output capacitor value & esr). b. error amplifier compensation & saw-tooth wave amplitude (compensation network). c. kelvin sense for v core . current loop setting a. gm amplifier s/h current (current sense component dcr, isp x and isn x pin external resistor value). b. over-current protection trip point (r imax resistor). vrm load line setting a. droop amplitude (adj pin resistor). b. no load offset (r csn ) c. dac offset voltage setting (ofs pin & compensation network resistor). d. temperature coefficient compensation(tsen external resister & thermistor, resistor between adj and gnd.) power sequence & ss dvd pin external resistor and ss pin capacitor. pcb layout a.kelvin sense for current sense gm amplifier input. b.refer to layout guide for other items. ch1:(500mv/div) ch2:(2v/div) ea rising slew rate time (250ns/div) v comp v fb ch1:(500mv/div) ch2:(2v/div) ea falling slew rate time (250ns/div) v comp v fb
rt8803a 27 ds8803a-06 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 32l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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